SSTUA32866 Datasheet (NXP) - configurable registered buffer

SSTUA32866, configurable registered buffer

The SSTUA32866 is a 1.8 V conﬁgurable register speciﬁcally designed for use on DDR2 memory modules requiring a parity checking function.

It is deﬁned in accordance with the JEDEC standard for the SSTUA32866 registered buffer.

The register is conﬁgurable (using conﬁguration pins C0 and C1) to two top

SSTUA32866 Features

* s s s s s s s s s s s s s s Conﬁgurable register supporting DDR2 up to 667 MT/s Registered DIMM applications Conﬁgurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode Controlled output impedance drivers enable optimal signal integrity and speed Exceeds JESD82-7 speed performance (1.8 ns max. single-bit