SSTUB32866 Datasheet - NXP

SSTUB32866 configurable registered buffer

The SSTUB32866 is a 1.8 V conﬁgurable register speciﬁcally designed for use on DDR2 memory modules requiring a parity checking function. It is deﬁned in accordance with the JEDEC standard for the SSTUB32866 registered buffer. The register is conﬁgurable (using conﬁguration pins C0 and C1) to two top.

SSTUB32866 Features

* I I I I I I I I I I I I I I Conﬁgurable register supporting DDR2 up to 800 MT/s Registered DIMM applications Conﬁgurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode Controlled output impedance drivers enable optimal signal integrity and speed Meets or exceeds SSTUB32866 JEDEC standard speed performanc

SSTUB32866_PhilipsSemiconductors.pdf