SSTUB32868 Datasheet - NXP

SSTUB32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity

The SSTUB32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally require.

SSTUB32868 Features

* 28-bit data register supporting DDR2

* Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (that is, 2 × SSTUA32864 or 2 × SSTUA32866)

* Parity checking function across 22 input data bits

* Parity out signal

SSTUB32868_PhilipsSemiconductors.pdf