SSTUB32868

1.8 V 28-bit 1 : 2 configurable registered buffer with parity

NXP

SSTUB32868 Features

* 28-bit data register supporting DDR2

* Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (that is, 2 × SSTUA32864 or 2 × SSTUA32866)

* Parity checking function across 22 input data bits

* Parity out signal

SSTUB32868 General Description

The SSTUB32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally require.

SSTUB32868 Datasheet (301.87 KB)

SSTUB32868 Datasheet Preview — Preview of SSTUB32868 PDF

Datasheet Details

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SSTUB32868

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NXP ↗

File Size:

301.87 KB

Description:

1.8 v 28-bit 1 : 2 configurable registered buffer with parity.
www.DataSheet4U.com SSTUB32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 04

* 22 Apr.

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SSTU32866 1.8V 25-bit 1:1 or 14-bit 1:2 confgurable registered buffer (NXP)

SSTUA32864 configurable registered buffer (NXP)

SSTUA32866 configurable registered buffer (NXP)

SSTUH32864 1.8 V high output drive configurable registered buffer (NXP)

SSTUH32865 1.8V 28-bit high output drive 1:2 registered buffer (NXP)

SSTUH32866 1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer (NXP)

SSTUM32865 1.8 V 28-bit 1 : 2 registered buffer (NXP)

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SSTUB32868 1.8 28-bit configurable registered buffer with parity NXP

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SSTUB32868 Features

SSTUB32868 General Description

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