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DS90LV110AT 1 to 10 LVDS Data/Clock Distributor

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Description

DS90LV110AT 1 to 10 LVDS Data/Clock Distributor with Failsafe www.DataSheet4U.com September 19, 2008 DS90LV110AT 1 to 10 LVDS Data/Clock Distributo.
DS90LV110A is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation.

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Datasheet Specifications

Part number
DS90LV110AT
Manufacturer
National Semiconductor
File Size
1.25 MB
Datasheet
DS90LV110AT_NationalSemiconductor.pdf
Description
1 to 10 LVDS Data/Clock Distributor

Features

* Low jitter 400 Mbps fully differential data path
* 145 ps (typ) of pk-pk jitter with PRBS = 223
* 1 data pattern
* at 400 Mbps Single +3.3 V Supply Balanced output impedance Output channel-to-channel skew is 35ps (typ) Differe

Applications

* for higher speed links with improved signal quality. It can also be used for clock distribution up to 200MHz. The DS90LV110A accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks. The LVDS outputs can be put into TRI-STATEĀ® by use of the enable pin. For more details, p

DS90LV110AT Distributors

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