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NLA9535 - Low-Power 16-bit I/O Expander

Datasheet Summary

Description

Pin Symbol SOIC24, TSSOP24 INT 1 AD1 2 AD2 3 IO0_0 4 IO0_1 5 IO0_2 6 IO0_3 7 IO0_4 8 IO0_5 9 IO0_6 10 IO0_7 11 VSS 12 IO1_0 13 IO1_1 14 IO1_2 15 IO1_3 16 IO1_4 17 IO1_5 18 IO1_6 19 IO1_7 20 AD0 21 SCL 22 SDA 23 VDD 24 WQFN24 22 23 24 1

Features

  • VDD Operating Range: 1.65 V to 5.5 V.
  • SDA Sink Capability: 30 mA.
  • 5.5 V Tolerant I/Os.
  • Polarity Inversion Register.
  • Active LOW Interrupt Output.
  • Low Standby Current.
  • Noise Filter on SCL/SDA Inputs.
  • No Glitch on Power-up, Internal Power-on Reset.
  • 64 Programmable Target Addresses Using Three Address Pins.
  • 16 I/O Pins Which Default to 16 Inputs.
  • I2C SCL Clock Frequencies Supported: Standard Mode: 100.

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Datasheet preview – NLA9535

Datasheet Details

Part number NLA9535
Manufacturer ON Semiconductor
File Size 230.60 KB
Description Low-Power 16-bit I/O Expander
Datasheet download datasheet NLA9535 Datasheet
Additional preview pages of the NLA9535 datasheet.

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Full PDF Text Transcription

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Low-Power 16-bit I/O Expander for I2C Bus with Interrupt Product Preview NLA9535, NLA9535C The NLA9535 and NLA9535C provide 16 bits of General Purpose parallel Input / Output (GPIO) expansion through the I2C-bus / SMBus. The devices consist of two 8-bit Configuration (Input or Output selection); Input, Output and Polarity Inversion (active-HIGH or active-LOW operation) registers. At power on, all I/Os default to inputs. Each I/O may be configured as either input or output by writing to its corresponding I/O configuration bit. The data for each Input or Output is kept in its corresponding Input or Output register. The Polarity Inversion register may be used to invert the polarity of the read register. All registers can be read by the system controller.
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