Description
m PLL205-03 o c .Motherboard Clock Generator for AMD - K7 U 4 t e .
Name
VDD0 VDD1 VDD2 VDD3 VDD4 GND XIN XOUT REF0//CPU_STOP
Number
1 6 14 19,30,36,42 27 3,9,16,22, 33,39,45,47 4 5 2
Type
P P P P P P I O B Power su.
Features
* PIN CONFIGURATION e h
* Generates all clock frequencies for VIA K7 chip S sets requiring ta multiple CPU clocks and high speed a SDRAM buffers.
* Support one pair of differential CPU clocks, one . D 3.3V push-pull CPU clock, 6 PCI and 13 highw speed SDRAM buffers for 3-DIMM applicatio
Applications
* w w
* One 24_48MHz clock and one 48MHz clock.
* Two14.318MHz reference clocks. Power management control to stop CPU, and Power down Mode from I2C programming. Support 2-wire I2C serial bus interface with builtin Ve