PLL205-14 Datasheet (PhaseLink) - Programmable Clock Generator

PLL205-14, Programmable Clock Generator

Name VDD1 VDD2 VDD3 VDD4 VDDL1 VDDL2 GND XIN XOUT PD# PCI_STOP/ WDRESET# CPU_STOP AGP_STOP REF_STOP PCI(0:8) Number 1 5 15,23 25 40 33 2,8,12,19,29, 32,37,43 3 4 34 35 36 44 45 10,11,13,14, 16,17,18,20,21 Type P P P P P P P I O I B I I I O Description Power supply for REF(0:1), REF_F and crystal

PLL205-14 Features

* PIN CONFIGURATION e e frequencies for VIA KT266

* Generates all clock h chipset. S a

* Support one t pair of differential CPU clocks, one pair of a differential push-pull CPU clocks, 3 AGP and 10 PCI. D .

* w Enhanced PCI Output Drive selectable by I2C.

* w One 48MHz c