PLL205-14 Datasheet, Generator, PhaseLink

✔ PLL205-14 Features

PIN CONFIGURATION e e frequencies for VIA KT266
Generates all clock h chipset. S a
Support one t pair of differential CPU clocks, one pair of a differential push-pull

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PLL205-14

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PhaseLink

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📄 Datasheet

Description:

Programmable clock generator. Name VDD1 VDD2 VDD3 VDD4 VDDL1 VDDL2 GND XIN XOUT PD# PCI_STOP/ WDRESET# CPU_STOP AGP_STOP REF_STOP PCI(0:8) Number 1 5 15,23 25 40

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PLL205-14 Programmable Clock Generator PhaseLink