K4D553238F-JC Datasheet - Samsung

K4D553238F-JC 256Mbit GDDR SDRAM

K4D553238F-JC 256M GDDR SDRAM 256Mbit GDDR SDRAM 2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL (144-Ball FBGA) Revision 1.0 March 2004 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev 1.0 (Mar. 2004) K4D553238F-JC Revision History Revision 1.0 (March 8, 2004) DC Specification finalized 256M GDDR SDRAM Revision 0.1 (March 2 , 2004) - Target Spec Revision 0.0 (October 28.

K4D553238F-JC Features

* 2.5V + 5% power supply for device operation

* 2.5V + 5% power supply for I/O interface

* SSTL_2 compatible inputs/outputs

* 4 banks operation

* MRS cycle with address key programs -. Read latency 3, 4 (clock) -. Burst length (2, 4 and 8) -. Burst type (seque

K4D553238F-JC_Samsungsemiconductor.pdf