THC63LVD104S Datasheet - THine Electronics

THC63LVD104S 112MHz 30Bits Color LVDS Receiver

The THC63LVD104S receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104S converts the LVDS data streams back into 35bits of CMOS/TTL data with rising edge or falling edge clock for convenient with a variety of LCD.

THC63LVD104S Features

* Wide dot clock range: 8-112MHz suited for NTSC, VGA, SVGA, XGA, and SXGA

* PLL requires no external components 50% output clock duty cycle TTL clock edge and position programmable(3 step) Power down mode Low po

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