74HC138D Datasheet - Toshiba

74HC138D 3-to-8 Line Decoder

* 3-to-8 Line Decoder 2. General The 74HC138D is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inpu.

74HC138D Features

* (1) High speed: tpd = 16 ns (typ.) at VCC = 5 V (2) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25  (3) Balanced propagation delays: tPLH ≈ tPHL (4) Wide operating v

74HC138D-Toshiba.pdf