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DS90C032 LVDS Quad CMOS Differential Line Receiver

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Description

DS90C032 www.ti.com SNLS094D * JUNE 1998 * REVISED APRIL 2013 DS90C032 LVDS Quad CMOS Differential Line Receiver Check for Samples:.
TheDS90C032 is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.

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Features

* 1
* 2 >155.5 Mbps (77.7 MHz) switching rates
* Accepts small swing (350 mV) differential signal levels
* Ultra low power dissipation
* 600 ps maximum differential skew (5V, 25°C)
* 6.0 ns maximum propagation delay
* Industrial operating temperature rang

Applications

* requiring ultra low power dissipation and high data rates. The device supports data rates in excess of 155.5 Mbps (77.7 MHz) and uses Low Voltage Differential Signaling (LVDS) technology. TheDS90C032 accepts low voltage (350 mV) differential input signals and translates them to CMOS (TTL compatible)

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