DS90CR286AT-Q1 Datasheet (Texas Instruments) - 3.3 V Rising Edge Data Strobe LVDS Receiver

DS90CR286AT-Q1, 3.3 V Rising Edge Data Strobe LVDS Receiver

The DS90CR286AT-Q1 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data.

The receiver data outputs strobe on the output clock's rising edge.

The receiver LVDS clock operates at rates from 20 to 66 MHz.

The DS90CR286AT-Q1 phase-locks

DS90CR286AT-Q1 Features

* 1 20 to 66 MHz Shift Clock Support

* 50% Duty Cycle on Receiver Output Clock

* Best

* in

* Class Setup & Hold Times on Rx Outputs

* Rx Power Consumption < 270 mW (typ) at 66 MHz Worst Case

* Rx Power-down Mode < 200 μW (max)

* ESD Rating: