SCANPSC100F Datasheet (Texas Instruments) - Embedded Boundary Scan Controller

SCANPSC100F, Embedded Boundary Scan Controller

The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus.

It is useful in improving scan throughput when applying serial vectors to system test circuitry and reduces the software overhead that is associated with applying serial patterns with a parallel proc

SCANPSC100F Features

* 1

* 23 Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture

* Supported by Texas Instruments SCAN Ease (Embedded Application Software Enabler) Software

* Uses Generic, Asynchronous Processor Interface; Compatible with a Wide Range of Processo