74AUP2G79 Datasheet (nexperia) - Low-power dual D-type flip-flop

74AUP2G79, Low-power dual D-type flip-flop

The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop.

Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP).

The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable o

74AUP2G79 Features

* Wide supply voltage range from 0.8 V to 3.6 V

* High noise immunity

* Complies with JEDEC standards:

* JESD8-12 (0.8 V to 1.3 V)

* JESD8-11 (0.9 V to 1.65 V)

* JESD8-7 (1.2 V to 1.95 V)

* JESD8-5 (1.8 V to 2.7 V)

* JESD8-B (2.7 V to 3