INTEGRATED CIRCUITS DATA SHEET For a complete dat.
SN74HC11 - Triple 3-Input AND Gates
www.ti.com SCLS084E – DECEMBERSS19NN877244–HHRCCEV11I11S,,ESSDNNAP55R44IHHL CC20112111 SCLS084E – DECEMBER 1982 – REVISED APRIL 2021 SNx4HC11 Triple .TC74HC11AF - Triple 3-Input AND Gate
TC74HC11AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC11AP, TC74HC11AF Triple 3-Input AND Gate The TC74HC11A is a high speed.TC74HC11AP - Triple 3-Input AND Gate
TC74HC11AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC11AP, TC74HC11AF Triple 3-Input AND Gate The TC74HC11A is a high speed.TC74HC11AFN - Triple 3-Input AND Gate
TC74HC11AP/AF/AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC11AP,TC74HC11AF,TC74HC11AFN Triple 3-Input AND Gate The TC74HC11A .74HC11 - Triple 3-input AND gate
74HC11; 74HCT11 Triple 3-input AND gate Rev. 6 — 19 November 2015 Product data sheet 1. General description The 74HC11; 74HCT11 is a triple 3-input.MC74HC11A - Triple 3-Input AND Gate
MC74HC11A Triple 3-Input AND Gate High−Performance Silicon−Gate CMOS The MC74HC11A is identical in pinout to the LS11. The device inputs are compati.74HC11D - Triple 3-input AND gate
74HC11; 74HCT11 Triple 3-input AND gate Rev. 7 — 8 January 2021 Product data sheet 1. General description The 74HC11; 74HCT11 is a triple 3-input AN.HD74HC11 - Triple 3-input AND Gates
HD74HC11 Triple 3-input AND Gates Features • • • • • High Speed Operation: tpd = 9 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads .HD74HC112 - Dual J-K Flip-Flops
HD74HC112 Dual J-K Flip-Flops (with Preset and Clear) Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q out.HD74HC113 - Dual J-K Flip-Flops
HD74HC113 Dual J-K Flip-Flops (with Preset) Description This flip-flop is edge sensitive to the clock input and change state on the negative going tr.HD74HC114 - Dual J-K Flip-Flops
HD74HC114 Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock) Description This flip-flop is edge sensitive to the clock input and change.HD74HC11 - Triple 3-input AND Gates
HD74HC11 Triple 3-input AND Gates Features • High Speed Operation: tpd = 9 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wi.HD74HC112 - Dual J-K Flip-Flops
HD74HC112 Dual J-K Flip-Flops (with Preset and Clear) REJ03D0562-0200 (Previous ADE-205-435) Rev.2.00 Oct 11, 2005 Description Each flip-flop has ind.SL74HC11 - Triple 3-Input AND Gate
SL74HC11 Triple 3-Input AND Gate High-Performance Silicon-Gate CMOS The SL74HC11 is identical in pinout to the LS/ALS11. The device inputs are comp a.SL74HC112 - Dual J-K Flip-Flop with Set and Reset
SL74HC112 Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS The SL74HC112 is identical in pinout to the LS/ALS112. The device .M74HC11 - TRIPLE 3-INPUT AND GATE
M74HC11 TRIPLE 3-INPUT AND GATE s s s s s s s HIGH SPEED: tPD = 9ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C HIGH N.M74HC112 - DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
M54HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 67 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = .M74HC113 - DUAL J-K FLIP FLOP WITH PRESET
M54HC113 M74HC113 DUAL J-K FLIP FLOP WITH PRESET . . . . . . . . HIGH SPEED fMAX = 71 MHz (TYP.) at VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA at TA.MM74HC11 - Triple 3-Input AND Gate
MM54HC11 MM74HC11 Triple 3-Input AND Gate January 1988 MM54HC11 MM74HC11 Triple 3-Input AND Gate General Description These AND gates utilize advance.