SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop The SN74LS109A consists of two high speed completely independent transition clocked JK flip-flops

SN74LS109A Dual JK Positive Edge−Triggered Flip−Flop The SN74LS109A consists of two high speed completely independent transition clocked JK flip-flops

SN54/74LS10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERA

SN74LS10 TRIPLE 3-INPUT NAND GATE VCC 14 13 12 11 10 9 8 1234567 GND Symbol VCC Supply Voltage Parameter TA Operating Ambient Temperature Ra

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The c

DM74LS10 Triple 3-Input NAND Gate August 1986 Revised March 2000 DM74LS10 Triple 3-Input NAND Gate General Description This device contains three in

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device JM38510/30109BEA Status Package Type Package Pins Package

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output

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SN5410, SN54LS10, SN54S10, SN7410, SN74LS10, SN74S10 TRIPLE 3-INPUT POSITIVE-NAND GATES SDLS035A – DECEMBER 1983 – REVISED APRIL 2003 PRODUCTION DATA

SN54107, SN54LS107A, SN74107, SN74LS107A DUAL J-K FLIP-FLOPS WITH CLEAR SDLS036 – DECEMBER 1983 – REVISED MARCH 1988 PRODUCTION DATA information is c

DM54LS107A DM74LS107A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs June 1989 DM54LS107A DM74LS107A

www.DataSheet4U.com SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop The SN74LS109A consists of two high speed completely independent transition

www.ti.com PACKAGE OPTION ADDENDUM 4-Dec-2021 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan (1) Drawi

54LS109 DM54LS109A DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset Clear and Complementary Outputs June 1989 54LS109 DM54LS109A D

54LS10 DM54LS10 DM74LS10 Triple 3-Input NAND Gates June 1989 54LS10 DM54LS10 DM74LS10 Triple 3-Input NAND Gates General Description This device cont

DM74LS10 Triple 3-Input NAND Gate August 1986 Revised March 2000 DM74LS10 Triple 3-Input NAND Gate General Description This device contains three in

DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs June 1986 Revised March 2000 DM74LS109A Dual Pos

DM54LS107A DM74LS107A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs June 1989 DM54LS107A DM74LS107A