SN54/74LS10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INP.
Motorola
SN74LS109A - DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The c.
Motorola
SN74LS107A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output.
ON Semiconductor
74LS109A - LOW POWER SCHOTTKY
www.DataSheet4U.com SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop The SN74LS109A consists of two high speed completely independent transition .
Agere Systems
74LS109 - Dual J-K Flip-Flop
www.DataSheet4U.com www.DataSheet4U.com www.DataSheet4U.com www.DataSheet4U.com .
ON Semiconductor
SN74LS10 - TRIPLE 3-INPUT NAND GATE
SN74LS10 TRIPLE 3-INPUT NAND GATE VCC 14 13 12 11 10 9 8 1234567 GND Symbol VCC Supply Voltage Parameter TA Operating Ambient Temperature Ra.
Hitachi Semiconductor
HD74LS10 - Triple 3-input Positive NAND Gates
Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.
Hitachi Semiconductor
HD74LS107A - Dual J-K Negative-edge-triggered Flip-Flops
Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.
Hitachi Semiconductor
HD74LS109 - Dual J-K Positive-edge-triggered Flip-Flops
19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° Hit.
Hitachi Semiconductor
HD74LS109A - Dual J-K Positive-edge-triggered Flip-Flops
19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° Hit.
Renesas
HD74LS107A - Dual J-K Negative-edge-triggered Flip-Flops
HD74LS107A Dual J-K Negative-edge-triggered Flip-Flops (with Clear) REJ03D0425–0300 Rev.3.00 Jul.13.2005 Features • Ordering Information Part Name .
Renesas
HD74LS10 - Triple 3-Input Positive NAND Gates
HD74LS10 Triple 3-Input Positive NAND Gates Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviat.
Fairchild Semiconductor
DM74LS10 - Triple 3-Input NAND Gate
DM74LS10 Triple 3-Input NAND Gate August 1986 Revised March 2000 DM74LS10 Triple 3-Input NAND Gate General Description This device contains three in.
National Semiconductor
DM74LS10 - Triple 3-Input NAND Gates
54LS10 DM54LS10 DM74LS10 Triple 3-Input NAND Gates June 1989 54LS10 DM54LS10 DM74LS10 Triple 3-Input NAND Gates General Description This device cont.
Fairchild Semiconductor
DM74LS109A - Dual Positive-Edge-Triggered J-K Flip-Flop
DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs June 1986 Revised March 2000 DM74LS109A Dual Pos.
National Semiconductor
DM74LS109A - Dual Positive-Edge-Triggered J-K Flip-Flops
54LS109 DM54LS109A DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset Clear and Complementary Outputs June 1989 54LS109 DM54LS109A D.
ON Semiconductor
74LS10 - TRIPLE 3-INPUT NAND GATE
SN54/74LS10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERA.
Fairchild Semiconductor
74LS10 - Triple 3-Input NAND Gate
DM74LS10 Triple 3-Input NAND Gate August 1986 Revised March 2000 DM74LS10 Triple 3-Input NAND Gate General Description This device contains three in.
ON Semiconductor
SN74LS109 - LOW POWER SCHOTTKY
SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop The SN74LS109A consists of two high speed completely independent transition clocked JK flip-flops.
ON Semiconductor
SN74LS109A - Dual JK Positive Edge-Triggered Flip-Flop
SN74LS109A Dual JK Positive Edge−Triggered Flip−Flop The SN74LS109A consists of two high speed completely independent transition clocked JK flip-flops.
