DM74LS11 Triple 3-Input AND Gate August 1986 Revi.
Hitachi Semiconductor
HD74LS114 - Dual J-K Negative-edge-triggered Flip-Flops
Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.
Motorola
74LS112A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs.
Fairchild Semiconductor
74LS112A - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised March 2000 DM74.
Motorola
SN74LS11 - TRIPLE 3-INPUT AND GATE
TRIPLE 3-INPUT AND GATE SN54/74LS11 VCC 14 13 12 11 10 9 8 TRIPLE 3-INPUT AND GATE LOW POWER SCHOTTKY 1234567 GND GUARANTEED OPERATING RANGES .
Motorola
SN74LS113A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are desi.
Motorola
SN74LS112A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs.
Hitachi Semiconductor
HD74LS11 - Triple 3-input Positive AND Gates
Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.
Hitachi Semiconductor
HD74LS112 - Dual J-K Negative-edge-triggered Flip-Flops
19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° Hit.
Hitachi Semiconductor
HD74LS113 - Dual J-K Negative-edge-triggered Flip-Flops
Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.
Renesas
HD74LS112 - Dual J-K Negative-edge-triggered Flip-Flops
HD74LS112 Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear) REJ03D0426–0300 Rev.3.00 Jul.13.2005 Features • Ordering Information P.
Renesas
HD74LS11 - Triple 3-input Positive AND Gates
HD74LS11 / HD74LS15 Triple 3-input Positive AND Gates / Triple 3-input Positive AND Gates (with Open Collector Outputs) REJ03D0397–0300 Rev.3.00 Jul.1.
Fairchild Semiconductor
DM74LS11 - Triple 3-Input AND Gate
DM74LS11 Triple 3-Input AND Gate August 1986 Revised March 2000 DM74LS11 Triple 3-Input AND Gate General Description This device contains three inde.
National Semiconductor
DM74LS11 - Triple 3-Input AND Gates
54LS11 DM54LS11 DM74LS11 Triple 3-Input AND Gates June 1989 54LS11 DM54LS11 DM74LS11 Triple 3-Input AND Gates General Description This device contai.
Fairchild Semiconductor
DM74LS112A - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised March 2000 DM74.
Fairchild Semiconductor
74LS11 - Triple 3-Input AND Gate
DM74LS11 Triple 3-Input AND Gate August 1986 Revised March 2000 DM74LS11 Triple 3-Input AND Gate General Description This device contains three inde.
Hitachi Semiconductor
74LS112 - Dual J-K Negative-edge-triggered Flip-Flops
19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° Hit.
National Semiconductor
DM74LS112A - NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS
www.datasheet4u.com www.datasheet4u.com www.datasheet4u.com .
Motorola
SN74LS114A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS114A offers common clock and common clear inputs and individual J, K, and set in.
Motorola
74LS114A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS114A offers common clock and common clear inputs and individual J, K, and set in.
Texas Instruments
SN74LS112A - Dual J-K Negative-Edge-Triggered Flip-Flops
PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device JM38510/07102BEA Status Package Type Package Pins Package .
