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74112 - DUAL J-K FLIP FLOP
M54HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 67 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = .74175 - HEX/QUADRUPLE D-Type Flip-Flops
www.datasheet4u.com www.datasheet4u.com www.datasheet4u.com www.datasheet4u.com www.datasheet4u.com www.datasheet4u.com www.datasheet4u.com IMP.7474 - Dual Positive-Edge-Triggered D-Type Flip-Flops
DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs September 1986 Revised July 2001 DM7474 Dual Posi.7476 - Dual Master-Slave J-K Flip-Flops
DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs September 1986 Revised July 2001 DM7476 Dual Master-Slave J-K .4013 - Dual D-Type Flip-Flop
CD4013BC Dual D-Type Flip-Flop October 1987 Revised March 2002 CD4013BC Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop.74HC76 - DUAL J-K FLIP FLOP
M74HC76 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR HIGH SPEED : fMAX = 67MHz (TYP.) at VCC = 6V s LOW POWER DISSIPATION: www.DataSheet4U.comI CC =2µA(MA.74373 - 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops April 1986 Revised March 2000 DM74LS373 • DM74LS374 3-S.74LS74 - DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP
SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce.CD74HC107 - Dual J-K Flip-Flop
Data sheet acquired from Harris Semiconductor SCHS139D March 1998 - Revised October 2003 CD54HC107, CD74HC107, CD74HCT107 Dual J-K Flip-Flop with Res.TC4013BP - DUAL D-TYPE FLIP-FLOP
TC4013BP/BF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4013BP, TC4013BF TC4013B Dual D-Type Flip Flop TC4013B contains two independ.74173 - Quad 3-State D Flip-Flop
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad 3-State D Flip-Flop with Common Clock and Reset High–Performance Silicon–Gate CMOS The MC74HC173 is ident.HC273 - Octal-D Flip-Flop
SL74HC273 Octal D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS The SL74HC273 is identical in pinout to the LS/ALS273. The.K561TM2 - 2-stage (Master-slave) D flip-flop
Корпус: DIP-14 Микросхема К561ТМ2 представляет собой два двухступенчатых (master-slave) D-триггера со входами асинхронной установки и сброса и против.74109 - Dual J-K Positive-Edge-Triggered Flip-Flops
www.ti.com PACKAGE OPTION ADDENDUM 4-Dec-2021 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan (1) Drawi.SN7474 - Dual D-Type Positive-Edge Triggered Flip-Flops
SN5474, SN54LS74A, SN54S74 SN7474. SN74LS74A, SN74S74 DUAL DĆTYPE POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH PRESET AND CLEAR SDLS119 − DECEMBER 1983 − R.74HC112 - Dual J-K Negative-Edge-Triggered Flip-Flops
SN54HC112, SN74HC112 SCLS099H – DECEMBER 1982 – REVISED JUNE 2022 SNx4HC112 Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 1 Featu.74F174 - Hex D flip-flops
INTEGRATED CIRCUITS 74F174 Hex D flip-flops Product specification IC15 Data Handbook 1988 Oct 07 Philips Semiconductors Philips Semiconductors Pro.74107 - DUAL J-K FLIP-FLOP
M54HC107 M74HC107 DUAL J-K FLIP FLOP WITH CLEAR . . . . . . . . HIGH SPEED fMAX = 75 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.).74ACT109 - Dual JK Positive Edge-Triggered Flip-Flop
74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop March 2007 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Features ■ ICC re.