| Title | |
| Description | The 512Mb Double-Data-Rate-3 (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation. It is internally configured as an eight-bank DRAM. The 512Mb chip is organized as 4Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications. The chip is designed to comply with all key DD... |
| Features |
and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.35V -0.067V/+0.1V or...
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| Datasheet |
 M15T5121632A Datasheet - 7.24MB |
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