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EDD5116AFTA-5 - 512M bits DDR SDRAM

This page provides the datasheet information for the EDD5116AFTA-5, a member of the EDD5108AFTA-5 512M bits DDR SDRAM family.

Description

The EDD5108AFTA and the EDD5116AFTA are 512M bits Double Data Rate (DDR) SDRAM organized as 16,777,216 words × 8 bits × 4 banks and 8,388,608 words × 16 bits × 4 banks, respectively.

Read and write operations are performed at the cross points of the CK and the /CK.

Features

  • Power supply: VDD ,VDDQ = 2.6V ± 0.1V.
  • Data rate: 400Mbps (max. ).
  • Double Data Rate architecture; two data transfers per clock cycle.
  • Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver.
  • Data inputs, outputs, and DM are synchronized with DQS.
  • 4 internal banks for concurrent operation.
  • DQS is edge aligned with data for READs; center aligned with data for WRITEs.
  • Differential.

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Datasheet preview – EDD5116AFTA-5

Datasheet Details

Part number EDD5116AFTA-5
Manufacturer Elpida Memory
File Size 611.16 KB
Description 512M bits DDR SDRAM
Datasheet download datasheet EDD5116AFTA-5 Datasheet
Additional preview pages of the EDD5116AFTA-5 datasheet.

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Full PDF Text Transcription

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DATA SHEET 512M bits DDR SDRAM EDD5108AFTA-5 (64M words × 8 bits, DDR400) EDD5116AFTA-5 (32M words × 16 bits, DDR400) Description The EDD5108AFTA and the EDD5116AFTA are 512M bits Double Data Rate (DDR) SDRAM organized as 16,777,216 words × 8 bits × 4 banks and 8,388,608 words × 16 bits × 4 banks, respectively. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. They are packaged in standard 66-pin plastic TSOP (II). Pin Configurations /xxx indicates active low signal.
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