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FDC636P - P-Channel MOSFET

General Description

These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology.

This very high density process is especially tailored to minimize on-state resistance.

Key Features

  • -2.8 A, -20 V. RDS(ON) = 0.130 Ω @ VGS = -4.5 V RDS(ON) = 0.180 Ω @ VGS = -2.5 V. SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 S D D 1 6 .63 6 2 5 G SuperSOT TM pin 1 D D 3 4 -6 Absolute Maximum Ratings T A = 25°C unless otherwise noted Symbol Parameter VDSS V.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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May 1998 FDC636P P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as cellular phone and notebook computer power management and other battery powered circuits where high-side switching, and low in-line power loss are needed in a very small outline surface mount package. Features -2.8 A, -20 V. RDS(ON) = 0.130 Ω @ VGS = -4.5 V RDS(ON) = 0.180 Ω @ VGS = -2.5 V.