KM736V687A Datasheet | Samsung Semiconductor

FEATURES - Synchronous Operation. - On-Chip Address Counter. - Write Self-Timed Cycle. - On-Chip Address and Control Registers. - VDD= 3.3V+0.3V/-0.165V Power Supply. - VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. - 5V Tolerant Inputs except I/O Pins. - Byte Writable Function. - Global Write Enable Controls a full bus-width write. - Power Down State via ZZ Signal. - Asynchronous Output Enable Control. - ADSP, ADSC, ADV Burst Control Pins. - LBO Pin allows a choice of either a interleaved burst or a linear burst. - Three Chip Enables for simple depth expansion with No Data Contention. - TTL-Level Three-State Output. - 100-TQFP-1420A 64Kx36 Synchronous SRAM GENERAL DESCRIPTION The KM736V687A is 2,359,296 bits Synchronous Static Random Access Memory designed to support zero wait state performance for advanced Pentium/Power PC based system. And with CS1 high, ADSP is blocked to control signals. It can be organized as 64K words of 36 bits. And it integrates address and control registers, a 2-bit burst address counter and high output drive circuitry onto a single integrated circuit for reduced ponents counts implementation of high performance cache RAM applications. Write cycles are internally self-timed and synchronous. The self-timed write feature eliminates plex off chip write pulse shaping logic, simplifying the cache design and further reducing the ponent count. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the system′s burst sequence and are controlled by the burst address advance(ADV) input. ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The KM736V687A is...