CY7C1212H - 1-Mbit (64K x 18) Pipelined Sync SRAM
1] The CY7C1212H SRAM integrates 64K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.
All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).
The synchronous inputs include all addresse
CY7C1212H Features
* Registered inputs and outputs for pipelined operation
* 64K × 18 common I/O architecture
* 3.3V core power supply (VDD)
* 2.5V/3.3V I/O power supply (VDDQ)
* Fast clock-to-output times
* 3.5 ns (for 166-MHz device)
* Provide high-performance
