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CY7C1212F - 1-Mbit (64K x 18) Pipelined Sync SRAM

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Datasheet Details

Part number CY7C1212F
Manufacturer Cypress Semiconductor
File Size 359.67 KB
Description 1-Mbit (64K x 18) Pipelined Sync SRAM
Datasheet download datasheet CY7C1212F_CypressSemiconductor.pdf

CY7C1212F Product details

Description

1] The CY7C1212F SRAM integrates 65,536 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B], and BWE), and Global Write

Features

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