CY7C1214F - 1-Mb (32K x 32) Flow-Through Sync SRAM
1] The CY7C1214F is a 32,768 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic.
Maximum access delay from clock rise is Logic Block Diagram A0, A1, A ADDRESS REGISTER A[1:0] MODE ADV CLK BURST Q1 COUNTER AND LOGIC Q0 CLR ADSC ADSP DQD BWD B
CY7C1214F Features
* 32K X 32 common I/O
* 3.3V
* 5% and +10% core power supply (VDD)
* 3.3V I/O supply (VDDQ)
* Fast clock-to-output times
* 7.5 ns (117-MHz version)
* 8.5 ns (100-MHz version)
* Provide high-performance 2-1-1-1 access rate
* User-
