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CY7C1219F

1-Mbit (32K x 36) Pipelined DCD Sync SRAM

CY7C1219F Features

* Registered inputs and outputs for pipelined operation

* Optimal for performance (Double-Cycle deselect)

* Depth expansion without wait state

* 32K × 36-bit common I/O architecture

* 3.3V

* 5% and +10% core power supply (VDD)

* 3.3V I/O supply

CY7C1219F General Description

1] The CY7C1219F SRAM integrates 32,768 x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addre.

CY7C1219F Datasheet (375.20 KB)

Preview of CY7C1219F PDF

Datasheet Details

Part number:

CY7C1219F

Manufacturer:

Cypress Semiconductor

File Size:

375.20 KB

Description:

1-mbit (32k x 36) pipelined dcd sync sram.

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TAGS

CY7C1219F 1-Mbit 32K Pipelined DCD Sync SRAM Cypress Semiconductor

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