CY7C1223F Datasheet (Cypress Semiconductor) - 2-Mb (128K x 18) Pipelined DCD Sync SRAM

CY7C1223F, 2-Mb (128K x 18) Pipelined DCD Sync SRAM

1] The CY7C1223F SRAM integrates 131,072 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

The synchronous inputs include all addr

CY7C1223F Features

* Registered inputs and outputs for pipelined operation

* Optimal for performance (Double-Cycle deselect)

* Depth expansion without wait state

* 128K × 18-bit common I/O architecture

* 3.3V

* 5% and +10% core power supply (VDD)

* 3.3V I/O supply