Datasheet Details
| Part number | CY7C1223F |
|---|---|
| Manufacturer | Cypress Semiconductor |
| File Size | 493.46 KB |
| Description | 2-Mb (128K x 18) Pipelined DCD Sync SRAM |
| Datasheet |
 CY7C1223F_CypressSemiconductor.pdf
|
| Part number | CY7C1223F |
|---|---|
| Manufacturer | Cypress Semiconductor |
| File Size | 493.46 KB |
| Description | 2-Mb (128K x 18) Pipelined DCD Sync SRAM |
| Datasheet |
CY7C1223F_CypressSemiconductor.pdf
|
1] The CY7C1223F SRAM integrates 131,072 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B] and BWE), and Global Write
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