CY7C1231F Datasheet (Cypress Semiconductor)

CY7C1231F, 2Mbit Flow-Through SRAM

1] CY7C1231F 2-Mbit (128K x 18) Flow-through SRAM with NoBL™ Architecture The CY7C1231F is a 3.3V, 128K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

The CY7C1231F is equipped with t

CY7C1231F Features

* Can support up to 117-MHz bus operations with zero wait states

* Data is transferred on every clock w w

* Pin compatible and functionally equivalent to ZBT™ devices

* Internally self-timed output buffer control to eliminate the need to use OE

* Registere