CY7C1250KV18 Datasheet - Cypress Semiconductor

CY7C1250KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture

CY7C1250KV18 Features

* 36-Mbit density (2M × 18, 1M × 36)

* 450 MHz clock for high bandwidth

* Two-word burst for reducing address bus frequency

* Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz

* Available in 2.0 clock cycle latency

* Two input clocks (K and K) for pre

Datasheet Details

CY7C1250KV18

Cypress Semiconductor

1.17 MB

36-mbit ddr ii+ sram two-word burst architecture.

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