* Separate independent read and write data ports
* Supports concurrent transactions
* 550-MHz clock for high bandwidth
* Four-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
CY7C1665KV18 Datasheet (1.20 MB)
CY7C1665KV18
Cypress Semiconductor
1.20 MB
144-mbit qdr ii+ sram four-word burst architecture.
CY7C1663KV18/CY7C1665KV18 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 144-Mbit QDR® II+ SRAM Four-Word Burst Archite.
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