* JEDEC Standard VDD/VDDQ = 1.5V±0.075V.
* All inputs and outputs are compatible with SSTL_15 interface.
* Fully differential clock inputs (CK, /CK) operation.
* Eight Banks
* Posted CAS by programmable additive latency
* Bust length: 4 with Burst Chop
EM47EM0888SBA Datasheet (618.87 KB)
EM47EM0888SBA
Eorex
618.87 KB
4gb double data rate-3 sdram.
Revision History
Revision 0.1 (Oct. 2011) -First release.
EM47EM0888SBA
Revision 0.2 (Apr. 2012) - Package dimension change
* delete 9 x 10..
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EM4 Electronic Indicator (ETC)
