* JEDEC Standard VDD/VDDQ = 1.5V±0.075V.
* All inputs and outputs are compatible with SSTL_15 interface.
* Fully differential clock inputs (CK, /CK) operation.
* Eight Banks
* Posted CAS by programmable additive latency: 0, CL-1 & CL-2
* Bust length: 4
EM47CM1688SBB Datasheet (592.13 KB)
EM47CM1688SBB
Eorex
592.13 KB
4gb double data rate-3 sdram.
Revision History
Revision 0.1 (Jun. 2012) -First release.
EM47CM1688SBB
Jun. 2012
1/38
www.eorex.com
EM47CM1688SBB
1Gb (8M×8Bank×16) Double DATA .
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