* JEDEC Standard VDD/VDDQ = 1.5V±0.075V.
* All inputs and outputs are compatible with SSTL_15 interface.
* Fully differential clock inputs (CK, /CK) operation.
* Eight Banks
* Posted CAS by programmable additive latency
* Bust length: 4 with Burst Chop
EM47EM1688SBC Datasheet (1.83 MB)
EM47EM1688SBC
Eorex
1.83 MB
4gb double data rate-3 sdram.
Revision History Revision 0.1 (Oct. 2014) -First release. EM47EM1688SBC Oct. 2014 1/37 www.eorex.com EM47EM1688SBC 4Gb (32M×8Bank×16) Double DATA.
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