* JEDEC Standard VDD/VDDQ = 1.5V±0.075V.
* All inputs and outputs are compatible with SSTL_15 interface.
* Fully differential clock inputs (CK, /CK) operation.
* Eight Banks
* Posted CAS by programmable additive latency
* Bust length: 4 with Burst Chop
EM47EM1688SBB Datasheet (1.39 MB)
EM47EM1688SBB
Eorex
1.39 MB
4gb double data rate-3 sdram.
Revision History
Revision 0.1 (Mar. 2012) -First release.
Revision 0.2 (Oct. 2013) -Add package size.
EM47EM1688SBB
Oct. 2013
1/39
www.eorex.com
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