* JEDEC Standard VDD/VDDQ = 1.5V±0.075V.
* All inputs and outputs are compatible with SSTL_15 interface.
* Fully differential clock inputs (CK, /CK) operation.
* Eight Banks
* Posted CAS by programmable additive latency
* Bust length: 4 with Burst Chop
EM47DM0888SBA Datasheet (598.61 KB)
EM47DM0888SBA
Eorex
598.61 KB
4gb double data rate-3 sdram.
Revision History
Revision 0.1 (May. 2011) -First release.
EM47DM0888SBA
May. 2011
1/39
www.eorex.com
EM47DM0888SBA
1Gb (16M×8Bank×8) Double DATA .
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