SY100S838 Datasheet - Micrel Semiconductor

SY100S838 CLOCK GENERATION CHIP

The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a diffe.

SY100S838 Features

* 3.3V and 5V power supply options

* 50ps output-to-output skew

* Synchronous enable/disable

* Master Reset for synchronization

* Internal 75KΩ input pull-down resistors

* Available in 20-pin SOIC package TRUTH TABLE CLK EN ZL ZZ H XX NOTES: Z = LOW-to-HIGH transition

SY100S838_MicrelSemiconductor.pdf