K7A201800B Description
K7A203600B K7A203200B K7A201800B Document Title Preliminary 64Kx36/x32 & 128Kx18 Synchronous SRAM 64Kx36 & 64Kx32 & 128Kx18-Bit Synchronous Pipeline.
The K7A203600B, K7A203200B and K7A201800B are 2,359,296-bit Synchronous Static Random Access Memory designed for high performance second level cache o.
K7A201800B Features
* Synchronous Operation.
* 2 Stage Pipelined operation with 4 Burst.
* On-Chip Address Counter.
* Self-Timed Write Cycle.
* On-Chip Address and Control Registers.
* VDD= 3.3V+0.3V/-0.165V Power Supply.
* VDDQ Supply Voltage 3.3V+0.3V/-0.165V fo
K7A201800B Applications
* GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address
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