K7A201800B - 64Kx36 & 64Kx32-Bit Synchronous Pipelined Burst SRAM
The K7A203600B, K7A203200B and K7A201800B are 2,359,296-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 64K(128K) words of 36/32(18) bits and integrates address and control registers, a 2-bit burst .
K7A203600B K7A203200B K7A201800B Document Title Preliminary 64Kx36/x32 & 128Kx18 Synchronous SRAM 64Kx36 & 64Kx32 & 128Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No 0.0 0.1 History 1. Initial draft 1. Add tCYC 250,225, 200MHz bin. Draft Date Dec. 10. 2001 Jan . 17. 2002 Remark Preliminary Preliminary The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics .
K7A201800B Features
* Synchronous Operation.
* 2 Stage Pipelined operation with 4 Burst.
* On-Chip Address Counter.
* Self-Timed Write Cycle.
* On-Chip Address and Control Registers.
* VDD= 3.3V+0.3V/-0.165V Power Supply.
* VDDQ Supply Voltage 3.3V+0.3V/-0.165V fo
