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K7A203200A 64Kx32-Bit Synchronous Pipelined Burst SRAM

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Description

www.DataSheet4U.com PRELIMINARY K7A203200A Document Title 64Kx32-Bit Synchronous Pipelined Burst SRAM, 64Kx32 Synchronous SRAM Revision History Rev.
The K7A203200A is a 2,097,152-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC bas.

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Datasheet Specifications

Part number
K7A203200A
Manufacturer
Samsung semiconductor
File Size
304.82 KB
Datasheet
K7A203200A_Samsungsemiconductor.pdf
Description
64Kx32-Bit Synchronous Pipelined Burst SRAM

Features

* Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter. Self-Timed Write Cycle. On-Chip Address

Applications

* GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address

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