K7A203600A Datasheet - Samsung semiconductor

K7A203600A 64Kx36-Bit Synchronous Pipelined Burst SRAM

The K7A203600A is a 2,359,296-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 64K words of 36bits and integrates address and control registers, a 2-bit burst address counter and added some new funct.

PRELIMINARY K7A203600A Document Title 64Kx36-Bit Synchronous Pipelined Burst SRAM 64Kx36 Synchronous SRAM Revision History Rev. No. 0.0 0.1 History Initial draft Change t OH Min value from 1.3 to 1.0 at tCYC 5.0 Change t HZC Min value from 1.3 to 1.0 at tCYC 5.0 Add tCYC 183MHz, 225MHz Change DC Characteristics. Icc value from 260mA to 280mA at -72 ISB1 value from 10mA to 20mA ISB2 value from 10mA to 20mA Final spec release. Add VDDQ Supply voltage( 2.5V ) Draft Date May. 19. 1998 July. 13. 19.

K7A203600A Features

* Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter. Self-Timed Write Cycle. On-Chip Address

K7A203600A Datasheet (413.70 KB)