TC74HC107AP, TC74HC107 Datasheet - Toshiba

TC74HC107AP Dual J-K Flip-Flop

TC74HC107AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC107AP, TC74HC107AF Dual J-K Flip Flop with Clear The TC74HC107A is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. In accordance with the logic levels applied to the J and K inputs, the outputs change state on the negative going transition of the clock pulse. CLR is i.

TC74HC107AP Features

* High speed: fmax = 75 MHz (typ.) at VCC = 5 V

* Low power dissipation: ICC = 2 μA (max) at Ta = 25°C

* High noise immunity: VNIH = VNIL = 28% VCC (min)

* Output drive capability: 10 LSTTL loads

* Symmetrical output impedance: |IOH| = IOL = 4 mA (min)

TC74HC107_Toshiba.pdf