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CY7C64013C - 8-bit One Time Programmable microcontroller
CY7C64013C CY7C64113C Full-Speed USB (12-Mbps) Function Full-Speed USB (12-Mbps) Function Features ■ ■ Functional Overview The CY7C64013C and CY7C6.CY7C443 - (CY7C441 / CY7C443) Clocked 512 x 9 / 2K x 9 FIFOs
43 www.DataSheet4U.com CY7C441 CY7C443 Clocked 512 x 9, 2K x 9 FIFOs Features • High-speed, low-power, first-in first-out (FIFO) memories • 512 x 9.CY7C4122KV13 - 144-Mbit QDR-IV XP SRAM
CY7C4122KV13/CY7C4142KV13 144-Mbit QDR™-IV XP SRAM 144-Mbit QDR™-IV XP SRAM Features Configurations ■ 144-Mbit density (8M × 18, 4M × 36) ■ Total R.CY7C1313BV18 - (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features • Separate Independent Read and Write dat.CY7C67200 - EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller
CY7C67200 EZ-OTG™ Programmable USB On-The-Go Host/Peripheral Controller Cypress Semiconductor Corporation Document #: 38-08014 Rev. *E • 3901 Nort.CY7C1523AV18 - 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522AV18, CY7C1529AV18 CY7C1523AV18, CY7C1524AV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description Th.CY7C1371KV33 - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1371KV33 CY7C1371KVE33 CY7C1373KV33 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with NoBL™ Architecture (With ECC) 18-Mbit (512K × 36/1M × 18) .CY7C4021KV13 - 72-Mbit QDR-IV HP SRAM
CY7C4021KV13/CY7C4041KV13 72-Mbit QDR™-IV HP SRAM 72-Mbit QDR™-IV HP SRAM Features ■ 72-Mbit density (4M ×18, 2M ×36) ■ Total Random Transaction Rate.CY7C964 - Bus Interface Logic Circuit
64 fax id: 5604 CY7C964 Bus Interface Logic Circuit Features • Comparators, counters, latches, and drivers minimize logic requirements for a variet.CY7C1355C - (CY7C1355C / CY7C1357C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
www.DataSheet4U.com PRELIMINARY CY7C1355C CY7C1357C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latenc.CY7C1470V33 - (CY7C147xV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM
www.DataSheet4U.com CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Features • Pin-comp.CY7C1371B - (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM
73B CY7C1371B CY7C1373B 512K x 36/1M x 18 Flow-Thru SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT devic.CY7C9335A - SMPTE-259M/DVB-ASI Descrambler/Framer-Controller
CY7C9335A SMPTE-259M/DVB-ASI Descrambler/Framer-Controller Features • Fully compatible with SMPTE-259M • Fully compatible with DVB-ASI • Operates fro.CY7C1214H - 1-Mbit (32K x 32) Flow-Through Sync SRAM
CY7C1214H www.DataSheet4U.com 1-Mbit (32K x 32) Flow-Through Sync SRAM Features • 32K X 32 common I/O • 3.3V core power supply (VDD) • 2.5V/3.3V I/O .CY7C53150 - Neuron Chip Network Processor
CY7C53150, CY7C53120 Neuron Chip Network Processor Features ■ Three 8-bit pipelined processors for concurrent processing of application code and netw.CY7C09279V - 3.3 V 16K / 32K / 64K x 16 / 18 Synchronous Dual-Port Static RAM
CY7C09269V/79V/89V CY7C09369V/89V 3.3 V 16K / 32K / 64K × 16 / 18 Synchronous Dual-Port Static RAM 3.3 V 16K / 32K / 64K × 16 / 18 Synchronous Dual-P.CY7C140 - 1K x 8 Dual-Port Static RAM
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 1K x 8 Dual-Port Static RAM Features ■ True dual-ported memory cells, which allow simultaneous r.CY7C63413 - Low-speed USB Peripheral Controller
CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Low-speed USB Peripheral Controller Cypress Semiconductor .CY7C1354BV25 - 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
CY7C1354BV25 CY7C1356BV25 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture Features • Pin-compatible and functionally equivalent to ZBT™ • .CY7C1321KV18 - 18-Mbit DDR II SRAM Four-Word Burst Architecture
CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features ■ 18-Mbit densit.