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DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs September 1986 Revised July 2001 DM7474 Dual Posi

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M54HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 67 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC =

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Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0

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DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS73A Dua

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Корпус: DIP-14 Микросхема К561ТМ2 представляет собой два двухступенчатых (master-slave) D-триггера со входами асинхронной установки и сброса и против

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SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are

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M54HC107 M74HC107 DUAL J-K FLIP FLOP WITH CLEAR . . . . . . . . HIGH SPEED fMAX = 75 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.)

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DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS73A Dua

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DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops April 1986 Revised March 2000 DM74LS373 • DM74LS374 3-S

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SN5472, SN7472 AND-GATED J-K MASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR SDLS117 – DECEMBER 1983 – REVISED MARCH 1988 PRODUCTION DATA information i

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal D Flip-Flop with Common Clock and Reset High–Performance Silicon–Gate CMOS The MC54/74HC273A is identica

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3-STATE Octal D-Type Flip-Flop MM74HC374 General Description The MM74HC374 high speed Octal D−Type Flip−Flops utilize advanced silicon−gate CMOS techn

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SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce

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www.ti.com SN54LVTH16374, SN74LVTH16374 3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS145R – MAY 1992 – REVISED AUGUST 2

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SN54ALS874B, SN74ALS874B, SN74ALS876A SN74AS874, SN74AS876 DUAL 4ĆBIT DĆTYPE EDGEĆTRIGGERED FLIPĆFLOPS SDAS061C − APRIL 1982 − REVISED JANUARY 1995 •

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SN5472, SN7472 AND-GATED J-K MASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR SDLS117 – DECEMBER 1983 – REVISED MARCH 1988 PRODUCTION DATA information i

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DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs September 1986 Revised July 2001 DM7476 Dual Master-Slave J-K

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HEF4027B Dual JK flip-flop Rev. 12 — 8 August 2024 Product data sheet 1. General description The HEF4027B is a dual positive-edge triggered JK flip-

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Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0

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