Flip-FLop Datasheet | Specifications & PDF Download

HD74HC114 Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock) Description This flip-flop is edge sensitive to the clock input and change

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74HC574 Octal 3−State Noninverting D Flip−Flop High−Performance Silicon−Gate CMOS The 74HC574 is identical in pinout to the LS574. The device inputs a

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74HC574; 74HCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 7 — 4 March 2016 Product data sheet 1. General description The 74HC

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DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D

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5476 DM5476 DM7476 Dual Master-Slave J-K Flip-Flops with Clear Preset and Complementary Outputs June 1989 5476 DM5476 DM7476 Dual Master-Slave J-K F

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54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs June 1989 54LS74 DM54LS74A DM74LS74

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54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs June 1989 54LS74 DM54LS74A DM74LS74

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M54HC107 M74HC107 DUAL J-K FLIP FLOP WITH CLEAR . . . . . . . . HIGH SPEED fMAX = 75 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.)

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SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS

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M54HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 67 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC =

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DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS74A Dual Posit

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Signetics 74L5373, 74L5374, 5373, 5374 Latches/Flip-Flops Logic Products '373 Octal Transparent Latch With 3-State Outputs '374 Octal D Flip-Flop W

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TC4013BP/BF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4013BP, TC4013BF TC4013B Dual D-Type Flip Flop TC4013B contains two independ

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SN74LS373, SN74LS374 Octal Transparent Latch with 3−State Outputs; Octal D−Type Flip−Flop with 3−State Output The SN74LS373 consists of eight latches

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CD4013BC Dual D-Type Flip-Flop October 1987 Revised March 2002 CD4013BC Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop

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SN74LS373, SN74LS374 Octal Transparent Latch with 3−State Outputs; Octal D−Type Flip−Flop with 3−State Output The SN74LS373 consists of eight latches

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DM54LS373 DM74LS373 DM54LS374 DM74LS374 TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops May 1992 DM54LS373 DM74LS373 DM54LS

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DATASHEET CD40174BMS CMOS Hex ‘D’-Type Flip-Flop Rev X.00 Jan 13, 2017 Features • High Voltage Type (20V Rating) • 5V, 10V and 15V Parametric Ratin

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DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS73A Dua

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74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Rev. 7 — 6 September 2021 Product data sheet 1. General description The

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