ICS8752 buffer equivalent, lvcmos clock multiplier/zero delay buffer.
* Fully integrated PLL
* Eight LVCMOS outputs, 7Ω typical output impedance
* Selectable LVCMOS CLK0 or CLK1 inputs for redundant clock applications
* Inpu.
The CLK_SEL input determines which reference clock is used. The output divider values of Bank A and B are controlled by.
Image gallery
Download