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CY7C1148KV18

18-Mbit DDR II+ SRAM Two-Word Burst Architecture

CY7C1148KV18 Features

* 18-Mbit density (1M × 18, 512K × 36)

* 450-MHz clock for high bandwidth

* Two-word burst for reducing address bus frequency

* Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz

* Available in 2.0 clock cycle latency

* Two input clocks (K and K) for p

CY7C1148KV18 Datasheet (610.31 KB)

Preview of CY7C1148KV18 PDF

Datasheet Details

Part number:

CY7C1148KV18

Manufacturer:

Cypress Semiconductor

File Size:

610.31 KB

Description:

18-mbit ddr ii+ sram two-word burst architecture.
CY7C1148KV18/CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 18-Mbit DDR II+ SRAM Two-Word Burst Architecture .

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CY7C1148KV18 18-Mbit DDR II + SRAM Two-Word Burst Architecture Cypress Semiconductor

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