CY7C1218F Datasheet (Cypress Semiconductor) - 1-Mb (32K x36) Pipelined Sync SRAM

CY7C1218F, 1-Mb (32K x36) Pipelined Sync SRAM

and Truth Table for further details).

Write cycles can be one to four bytes wide as controlled by the Byte Write control inputs.

GW when active LOW causes all bytes to be written.

The CY7C1218F operates from a +3.3V core power supply while all outputs may operate with a +3.3V supply.

All inputs and

CY7C1218F Features

* Registered inputs and outputs for pipelined operation

* 32K × 36 common I/O architecture

* 3.3V core power supply

* 3.3V I/O operation

* Fast clock-to-output times

* 3.5 ns (for 166-MHz device)

* 4.0 ns (for 133-MHz device)

* Provide