CY7C12701KV18 Datasheet - Cypress Semiconductor

CY7C12701KV18 1.8 V synchronous pipelined SRAM

CY7C12701KV18 Features

* 36-Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36)

* 550 MHz clock for high bandwidth

* 2-word burst for reducing address bus frequency

* Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz

* Available in 2.5 clock cycle latency

* Two input clock

Datasheet Details

CY7C12701KV18

Cypress Semiconductor

571.92 KB

1.8 v synchronous pipelined sram.

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