* Separate independent Read and Write data ports * Supports concurrent transactions * 167-MHz Clock for high bandwidth * 2.5 ns Clock-to-Valid access time * 2-Word Burst on all accesses * Double Data Rate (DDR) interfaces on both Read and Write Ports
CY7C1303BV18-CypressSemiconductor.pdf
Datasheet Details
CY7C1306BV18, CY7C1303BV18
Cypress Semiconductor
677.60 KB
18-mbit burst of 2 pipelined sram.
This datasheet PDF includes multiple part numbers: CY7C1306BV18, CY7C1303BV18.
Please refer to the document for exact specifications by model.
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