CY7C1418AV18, CY7C1416AV18 Datasheet (Cypress Semiconductor) - (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture

CY7C1418AV18, CY7C1416AV18, (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture

The CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, and CY7C1420AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture.

The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.

Addresses for Read and Write are latched on alternate ri

CY7C1418AV18 Features

* 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

* 250-MHz clock for high bandwidth

* 2-Word burst for reducing address bus frequency

* Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MHz

* Two input clocks (K and K) for precise DDR t