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CY7C1418KV18 36-Mbit DDR II SRAM Two-Word Burst Architecture

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Description

CY7C1418KV18/CY7C1420KV18 36-Mbit DDR II SRAM Two-Word Burst Architecture 36-Mbit DDR II SRAM Two-Word Burst Architecture .
The CY7C1418KV18, and CY7C1420KV18 are 1.

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Datasheet Specifications

Part number
CY7C1418KV18
Manufacturer
Cypress Semiconductor
File Size
777.80 KB
Datasheet
CY7C1418KV18-CypressSemiconductor.pdf
Description
36-Mbit DDR II SRAM Two-Word Burst Architecture

Features

* 36-Mbit density (2M × 18, 1M × 36)
* 333 MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
* Two input clocks (K and K) for precise DDR timing
* SRAM uses rising edge

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Cypress Semiconductor CY7C1418KV18-like datasheet